A serializer/deserializer (SERDES) equipped with a decision feedback based equalizer (DFE) requires scrambled, random data to effectively train the DFE taps. However, circuits and/or logics that accept recovered data from a SERDES have a conflicting requirement. The circuits and/or logics that accept recovered data require a predictable pattern (e.g., alignment character, comma character) at some interval to align recovered data to a known boundary. Balancing these requirements leads to compromises in speed, randomness, and other factors. In some cases, the compromises may be unacceptable.
One conventional approach known as 8b10b encoding uses the K28.4 “comma” character to align the SERDES data to a known boundary. Other conventional approaches continuously transmit a fixed 10-bit value until link align circuits and/or logics complete bit alignment. Continuously transmitting a fixed bit pattern is the exact opposite of transmitting scrambled, random data. Another conventional approach known as 64/66 continuously sends 64 bits of scrambled data followed by a known 2-bit pattern (e.g., 10, 01) until alignment is achieved. However, it is very likely that the 2-bit alignment pattern will also appear in the 64 bits of scrambled data. Therefore, aligning to the known 2-bit pattern can be time consuming as many erroneous 2-bit patterns may be recognized during alignment.